VHDL ATMEL Mega/Xmega IP core for FPGA/ASIC implementation.

 I decided to put hardware IP's and C/C++ and other libraries made by me on this platform because remain forever :) 

First I will provide a link to the the github project that will  evolve to the final version, and when steemit will provide a file  storage solution I will put it there ( to remain forever ). 

For short I make IP's and micro-controllers libraries for personal  projects, but most of these projects like 98% , libraries and IP's I  make free of use by anyone without any restrictions because I think that  the copyright laws are an impediment to evolution of humans. 

A little description of this IP is that is a very optimized Atmel  Mega/Xmega configurable for Reduced/Minimal/Classic 8K/Classic  128K/Enchanced 8K/ Enchanced 128K/Xmega core. 

Most of instructions that are executed in more than one clock are  optimized for execution in one clock execution or one clock less, the  speed without timing violation is 66Mhz but in reality run without errors at 100Mhz. 

You can read download even contribute with code here. 

I hope to be useful for someone :)